The present invention relates to an integrated circuit in complementary circuit technology comprising a substrate bias voltage generator in which field effect transistors of different channel types are provided, at least one of which field effect transistors is arranged in a doped semiconductor substrate of a first conductivity type and at least one second field effect transistor is arranged in a tub-shaped semiconductor zone of a second conductivity type in the semiconductor substrate, whereby the semiconductor zone is connected to a voltage supply and a terminal region of at least one first field effect transistor is charged with a ground potential and the semiconductor substrate is connected to the output of a substrate bias voltage generator to which the ground potential and the supply voltage are supplied and which biases the pn junction between the terminal region of the first field effect transistor lying at ground potential and the semiconductor substrate in the reverse direction.
2. Description of the Prior Art
Given circuits of the type set forth above, the semiconductor substrate does not lie at the ground potential V.sub.SS of the circuit, but at a substrate bias voltage V.sub.BB which is generated by way of a substrate bias voltage generator. Given a semiconductor substrate composed of p-conductive material which is provided with an inserted n-conductive, tub-shaped semiconductor zone, a negative substrate bias voltage of about -2 to -3 volts is applied. The source regions of field effect transistors which are provided on the semiconductor substrate outside of the tub-shaped semiconductor zone are thereby applied to the ground potential V.sub.SS.
At the moment the positive supply voltage V.sub.DD is switched on, the p-conductive semiconductor substrate is initially in a "floating" state in which it is disconnected from external potentials. It can thereby be temporarily charged to a positive bias voltage via depletion layer capacitances which are present, first, between the tub-shaped semiconductor zone and the substrate and, second, between the source regions lying on ground potential and the substrate, the positive bias voltage remains until the substrate bias voltage generator takes effect and it is replaced by the negative substrate bias voltage being gradually built up at the output thereof. During operation of the integrated circuit as well, however, larger currents which are sinked from the semiconductor substrate via the substrate bias voltage generator to a terminal of the latter lying at ground potential can lead to a positive bias voltage of the semiconductor substrate due to the voltage drop at the internal resistance of the substrate bias voltage generator. Positive bias voltages, however, represent a high safety risk for the integrated circuit since a "latch-up" effect can be triggered, this usually meaning the failure of the integrated circuit.
In order to understand the "latch-up" effect, it can be assumed that four successive semiconductor layers of alternating conductivity types are generally present between a terminal of a field effect transistor of the first channel type lying in the tub-shaped semiconductor zone and a terminal of a field effect transistor of the second channel type located outside of this zone on the semiconductor substrate, whereby the one terminal region of the first transistor forms the first semiconductor layer, the tub-shaped semiconductor zone forms the second semiconductor layer, the semiconductor substrate forms the third and the one terminal region of the second transistor forms the fourth semiconductor layer. Given a positive bias voltage of the semiconductor substrate, the pn junction between the third and fourth semiconductor layers can be biased to such a degree in the conducting direction that a current path arises between the mentioned transistor terminal, this being attributable to a parasitic thyristor effect within the four-layer structure. The current path then also remains after the positive substrate bias voltage disappears and can thermally overload the integrated circuit.